The subject invention generally concerns the field of range recognizers for test and measurement instruments, such as logic analyzers, or the like, and specifically concerns a range encoder in an integrated circuit that provides more ranges or requires fewer connection pins.
A range recognizer is a well-known circuit used in a logic analyzer trigger structures to identify input vectors that reside within a particular range of values. In such a range recognizer, two binary comparators are used to determine if an input vector lies between two predetermined boundaries. If data is sampled in more than one integrated circuit (IC or chip), the results produced by the comparators in a first one of the ICs must be passed to a second IC where it is combined with the results from second IC. This fact leads to the unfortunate situation that, the more range recognizers there are, the more IC pins and board space must be used.
A prior art range recognizer implementation used by Tektronix in the TLA 700 Logic Analyzer, requires twelve pins to convey signals to and from each of four range recognizers. That is, three pins per range recognizer are used to encode xe2x80x9cgreater thanxe2x80x9d, xe2x80x9clesser thanxe2x80x9d, or xe2x80x9cequal toxe2x80x9d the upper boundary and lower boundary.
As ICs become ever more complex, reduction of pin count and conservation of printed board space (commonly referred to a xe2x80x9creal estatexe2x80x9d) becomes critical. What is needed is a range recognizer that produces the desired range comparison signals while also reducing IC pin count and conserving printed board space.
A range recognizer arrangement in accordance with the subject invention, requires only five IC pins to convey an encoded signal from a group of four range recognizers, and requires only twelve IC pins to convey an encoded signal from a group of over one thousand range recognizers. The subject range recognizer arrangement includes circuitry for combining and monotonically sorting all of the predetermined range boundaries, rather than treating each range recognizer as a separate unit. A range recognizer arrangement in accordance with the subject invention is suitable for use with test and measurement instruments such as a logic analyzer or the like.